Added support for new Intel family/model names.
Added proper support for using Core2 machines as P4. Added support for identifying SSE 3/4.1/4.2/4A support on CPU.
This commit is contained in:
@ -1,5 +1,6 @@
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/*
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/*
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* Created on Jul 14, 2004
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* Created on Jul 14, 2004
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* Updated on Jan 8, 2011
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*/
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*/
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package freenet.support.CPUInformation;
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package freenet.support.CPUInformation;
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@ -129,11 +130,26 @@ public class CPUID {
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CPUIDResult c = doCPUID(1);
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CPUIDResult c = doCPUID(1);
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return c.EAX & 0xf;
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return c.EAX & 0xf;
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}
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}
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private static int getCPUFlags()
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private static int getEDXCPUFlags()
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{
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{
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CPUIDResult c = doCPUID(1);
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CPUIDResult c = doCPUID(1);
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return c.EDX;
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return c.EDX;
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}
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}
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private static int getECXCPUFlags()
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{
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CPUIDResult c = doCPUID(1);
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return c.ECX;
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}
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private static int getExtendedEDXCPUFlags()
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{
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CPUIDResult c = doCPUID(0x80000001);
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return c.EDX;
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}
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private static int getExtendedECXCPUFlags()
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{
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CPUIDResult c = doCPUID(0x80000001);
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return c.ECX;
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}
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//Returns a CPUInfo item for the current type of CPU
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//Returns a CPUInfo item for the current type of CPU
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//If I could I would declare this method in a interface named
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//If I could I would declare this method in a interface named
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@ -163,13 +179,25 @@ public class CPUID {
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return getCPUVendorID();
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return getCPUVendorID();
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}
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}
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public boolean hasMMX(){
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public boolean hasMMX(){
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return (getCPUFlags() & 0x800000) >0; //Bit 23
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return (getEDXCPUFlags() & 0x800000) >0; //EDX Bit 23
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}
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}
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public boolean hasSSE(){
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public boolean hasSSE(){
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return (getCPUFlags() & 0x2000000) >0; //Bit 25
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return (getEDXCPUFlags() & 0x2000000) >0; //EDX Bit 25
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}
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}
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public boolean hasSSE2(){
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public boolean hasSSE2(){
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return (getCPUFlags() & 0x4000000) >0; //Bit 26
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return (getEDXCPUFlags() & 0x4000000) >0; //EDX Bit 26
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}
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public boolean hasSSE3(){
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return (getEDXCPUFlags() & 0x1) >0; //ECX Bit 0
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}
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public boolean hasSSE41(){
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return (getEDXCPUFlags() & 0x80000) >0; //ECX Bit 19
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}
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public boolean hasSSE42(){
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return (getEDXCPUFlags() & 0x100000) >0; //ECX Bit 20
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}
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public boolean hasSSE4A(){
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return (getExtendedECXCPUFlags() & 0x40) >0; //Extended ECX Bit 6
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}
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}
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public boolean IsC3Compatible() { return false; }
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public boolean IsC3Compatible() { return false; }
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}
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}
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@ -301,9 +329,18 @@ public class CPUID {
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}
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}
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public boolean IsPentium4Compatible()
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public boolean IsPentium4Compatible()
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{
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{
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return getCPUFamily() >= 15;
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if (getCPUFamily() >= 15){
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return true;
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} else if (getCPUExtendedModel() == 1 && (getCPUFamily() == 6 && (getCPUModel() == 10 || getCPUModel() == 13))){
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return true;
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} else if (getCPUExtendedModel() == 1 && getCPUFamily() == 6 && getCPUModel() == 10){
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return true;
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} else {
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return false;
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}
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}
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}
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public String getCPUModelString() throws UnknownCPUException {
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public String getCPUModelString() throws UnknownCPUException {
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if (getCPUExtendedModel() == 0){
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if(getCPUFamily() == 4){
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if(getCPUFamily() == 4){
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switch(getCPUModel()){
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switch(getCPUModel()){
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case 0:
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case 0:
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@ -326,6 +363,8 @@ public class CPUID {
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return "486 DX/4-WB";
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return "486 DX/4-WB";
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}
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}
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}
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}
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}
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if (getCPUExtendedModel() == 0){
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if(getCPUFamily() == 5){
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if(getCPUFamily() == 5){
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switch(getCPUModel()){
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switch(getCPUModel()){
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case 0:
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case 0:
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@ -344,7 +383,9 @@ public class CPUID {
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return "Mobile Pentium MMX";
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return "Mobile Pentium MMX";
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}
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}
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}
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}
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}
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if(getCPUFamily() == 6){
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if(getCPUFamily() == 6){
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if (getCPUExtendedModel() == 0){
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switch(getCPUModel()){
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switch(getCPUModel()){
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case 0:
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case 0:
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return "Pentium Pro A-step";
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return "Pentium Pro A-step";
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@ -361,11 +402,28 @@ public class CPUID {
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case 8:
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case 8:
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return "Pentium III (Coppermine), Celeron w/SSE";
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return "Pentium III (Coppermine), Celeron w/SSE";
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case 9:
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case 9:
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return "Mobile Pentium III";
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return "Mobile Pentium III (Banias)";
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case 10:
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case 10:
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return "Pentium III Xeon (Cascades)";
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return "Pentium III Xeon (Cascades)";
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case 11:
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case 11:
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return "Pentium III (130 nm)";
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return "Pentium III (130 nm)";
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case 13:
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return "Mobile Pentium III (Dothan)";
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case 14:
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return "Mobile Core (Yonah)";
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case 15:
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return "Core 2 (Conroe)";
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}
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}
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if (getCPUExtendedModel() == 1){
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switch(getCPUModel()){
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case 10:
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return "Core i7";
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case 12:
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return "Atom";
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case 13:
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return "Xeon MP";
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}
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}
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}
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}
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}
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if(getCPUFamily() == 7){
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if(getCPUFamily() == 7){
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@ -384,6 +442,10 @@ public class CPUID {
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return "Pentium IV (130 nm)";
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return "Pentium IV (130 nm)";
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case 3:
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case 3:
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return "Pentium IV (90 nm)";
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return "Pentium IV (90 nm)";
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case 4:
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return "Pentium IV (90 nm)";
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case 6:
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return "Pentium IV (65 nm)";
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}
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}
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}
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}
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if(getCPUExtendedFamily() == 1){
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if(getCPUExtendedFamily() == 1){
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@ -407,7 +469,7 @@ public class CPUID {
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System.out.println("CPU Family: " + getCPUFamily());
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System.out.println("CPU Family: " + getCPUFamily());
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System.out.println("CPU Model: " + getCPUModel());
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System.out.println("CPU Model: " + getCPUModel());
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System.out.println("CPU Stepping: " + getCPUStepping());
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System.out.println("CPU Stepping: " + getCPUStepping());
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System.out.println("CPU Flags: " + getCPUFlags());
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System.out.println("CPU Flags: " + getEDXCPUFlags());
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CPUInfo c = getInfo();
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CPUInfo c = getInfo();
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System.out.println(" **More CPUInfo**");
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System.out.println(" **More CPUInfo**");
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@ -415,6 +477,10 @@ public class CPUID {
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System.out.println(" CPU has MMX: " + c.hasMMX());
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System.out.println(" CPU has MMX: " + c.hasMMX());
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System.out.println(" CPU has SSE: " + c.hasSSE());
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System.out.println(" CPU has SSE: " + c.hasSSE());
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System.out.println(" CPU has SSE2: " + c.hasSSE2());
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System.out.println(" CPU has SSE2: " + c.hasSSE2());
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System.out.println(" CPU has SSE3: " + c.hasSSE3());
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System.out.println(" CPU has SSE4.1: " + c.hasSSE41());
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System.out.println(" CPU has SSE4.2: " + c.hasSSE42());
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System.out.println(" CPU has SSE4A: " + c.hasSSE4A());
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if(c instanceof IntelCPUInfo){
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if(c instanceof IntelCPUInfo){
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System.out.println(" **Intel-info**");
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System.out.println(" **Intel-info**");
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System.out.println(" Is pII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible());
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System.out.println(" Is pII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible());
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@ -1,6 +1,6 @@
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/*
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/*
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* Created on Jul 16, 2004
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* Created on Jul 14, 2004
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*
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* Updated on Jan 8, 2011
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*/
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*/
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package freenet.support.CPUInformation;
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package freenet.support.CPUInformation;
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@ -42,5 +42,25 @@ public interface CPUInfo
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*/
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*/
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public boolean hasSSE2();
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public boolean hasSSE2();
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/**
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* @return true iff the CPU support the SSE3 instruction set.
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*/
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public boolean hasSSE3();
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/**
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* @return true iff the CPU support the SSE4.1 instruction set.
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*/
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public boolean hasSSE41();
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/**
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* @return true iff the CPU support the SSE4.2 instruction set.
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*/
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public boolean hasSSE42();
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/**
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* @return true iff the CPU support the SSE4A instruction set.
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*/
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public boolean hasSSE4A();
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public boolean IsC3Compatible();
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public boolean IsC3Compatible();
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}
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}
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