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Added AVX/AVX2/AVX512/TBM feature detection

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This commit is contained in:
dev
2015-05-19 12:31:15 +00:00
parent d5d4dbb078
commit 39cb60e72b
4 changed files with 116 additions and 43 deletions
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26
core/java/src/freenet/support/CPUInformation/AMDInfoImpl.java
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@ -23,9 +23,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
private static boolean isExcavatorCompatible;
// If modelString != null, the cpu is considered correctly identified.
private static final String smodel = identifyCPU();
public boolean IsK6Compatible(){ return isK6Compatible; }
public boolean IsK6_2_Compatible(){ return isK6_2_Compatible; }
@ -53,14 +50,14 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
public String getCPUModelString() throws UnknownCPUException
{
String smodel = identifyCPU();
if (smodel != null)
return smodel;
throw new UnknownCPUException("Unknown AMD CPU; Family="+CPUID.getCPUFamily() + '/' + CPUID.getCPUExtendedFamily()+
", Model="+CPUID.getCPUModel() + '/' + CPUID.getCPUExtendedModel());
}
private static String identifyCPU()
private String identifyCPU()
{
// http://en.wikipedia.org/wiki/Cpuid
// #include "llvm/Support/Host.h", http://llvm.org/docs/doxygen/html/Host_8cpp_source.html
@ -196,7 +193,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isK6_3_Compatible = true;
isAthlonCompatible = true;
isAthlon64Compatible = true;
isX64 = true;
switch (model) {
case 4:
modelString = "Athlon 64/Mobile XP-M";
@ -328,7 +324,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isK6_3_Compatible = true;
isAthlonCompatible = true;
isAthlon64Compatible = true;
isX64 = true;
switch (model) {
case 2:
modelString = "Phenom / Athlon / Opteron Gen 3 (Barcelona/Agena/Toliman/Kuma, 65 nm)";
@ -365,7 +360,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isK6_3_Compatible = true;
isAthlonCompatible = true;
isAthlon64Compatible = true;
isX64 = true;
switch (model) {
case 3:
modelString = "AMD Turion X2/Athlon X2/Sempron (Lion/Sable, 65 nm)";
@ -388,7 +382,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isK6_3_Compatible = true;
isAthlonCompatible = true;
isAthlon64Compatible = true;
isX64 = true;
modelString = "AMD APU model " + model;
}
break;
@ -401,7 +394,6 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isAthlonCompatible = true;
isAthlon64Compatible = true;
isBobcatCompatible = true;
isX64 = true;
switch (model) {
case 1:
// Case 3 is uncertain but most likely a Bobcat APU
@ -423,7 +415,10 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isAthlonCompatible = true;
isAthlon64Compatible = true;
isBulldozerCompatible = true;
isX64 = true;
if (!this.hasAVX()) {
modelString = "Bulldozer";
break;
}
if (model >= 0x50 && model <= 0x5F) {
isPiledriverCompatible = true;
isSteamrollerCompatible = true;
@ -433,7 +428,7 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isPiledriverCompatible = true;
isSteamrollerCompatible = true;
modelString = "Steamroller";
} else if (model >= 0x10 && model <= 0x1F) {
} else if ((model >= 0x10 && model <= 0x1F) || hasTBM()) {
isPiledriverCompatible = true;
modelString = "Piledriver";
} else {
@ -451,17 +446,10 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isAthlon64Compatible = true;
isBobcatCompatible = true;
isJaguarCompatible = true;
isX64 = true;
modelString = "Jaguar";
}
break;
}
return modelString;
}
public boolean hasX64()
{
return isX64;
}
}

75
core/java/src/freenet/support/CPUInformation/CPUIDCPUInfo.java
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@ -7,8 +7,6 @@ package freenet.support.CPUInformation;
*/
abstract class CPUIDCPUInfo implements CPUInfo
{
protected static boolean isX64 = false;
public String getVendor()
{
return CPUID.getCPUVendorID();
@ -16,45 +14,100 @@ abstract class CPUIDCPUInfo implements CPUInfo
public boolean hasMMX()
{
return (CPUID.getEDXCPUFlags() & 0x800000) != 0; //EDX Bit 23
return (CPUID.getEDXCPUFlags() & (1 << 23)) != 0; //EDX Bit 23
}
public boolean hasSSE(){
return (CPUID.getEDXCPUFlags() & 0x2000000) != 0; //EDX Bit 25
return (CPUID.getEDXCPUFlags() & (1 << 25)) != 0; //EDX Bit 25
}
public boolean hasSSE2()
{
return (CPUID.getEDXCPUFlags() & 0x4000000) != 0; //EDX Bit 26
return (CPUID.getEDXCPUFlags() & (1 << 26)) != 0; //EDX Bit 26
}
public boolean hasSSE3()
{
return (CPUID.getECXCPUFlags() & 0x1) != 0; //ECX Bit 0
return (CPUID.getECXCPUFlags() & (1 << 0)) != 0; //ECX Bit 0
}
public boolean hasSSE41()
{
return (CPUID.getECXCPUFlags() & 0x80000) != 0; //ECX Bit 19
return (CPUID.getECXCPUFlags() & (1 << 19)) != 0; //ECX Bit 19
}
public boolean hasSSE42()
{
return (CPUID.getECXCPUFlags() & 0x100000) != 0; //ECX Bit 20
return (CPUID.getECXCPUFlags() & (1 << 20)) != 0; //ECX Bit 20
}
public boolean hasSSE4A()
{
return (CPUID.getExtendedECXCPUFlags() & 0x40) != 0; //Extended ECX Bit 6
return (CPUID.getExtendedECXCPUFlags() & (1 << 6)) != 0; //Extended ECX Bit 6
}
/**
* @return true iff the CPU supports the AVX instruction set.
* @since 0.9.21
*/
public boolean hasAVX()
{
return (CPUID.getECXCPUFlags() & (1 << 28)) != 0 && //AVX: ECX Bit 28
(CPUID.getECXCPUFlags() & (1 << 27)) != 0; //XSAVE enabled by OS: ECX Bit 27
}
/**
* @return true iff the CPU supports the AVX2 instruction set.
* @since 0.9.21
*/
public boolean hasAVX2()
{
return hasAVX() &&
(CPUID.getExtendedEBXCPUFlags() & (1 << 5)) != 0; //Extended EBX Bit 5
}
/**
* @return true iff the CPU supports the AVX512 instruction set.
* @since 0.9.21
*/
public boolean hasAVX512()
{
return hasAVX() &&
(CPUID.getExtendedEBXCPUFlags() & (1 << 5)) != 0; //Extended EBX Bit 5
}
/**
* @return true iff the CPU supports the ADX instruction set.
* @since 0.9.21
*/
public boolean hasADX()
{
return hasAVX() &&
(CPUID.getExtendedEBXCPUFlags() & (1 << 19)) != 0; //Extended EBX Bit 19
}
/**
* @return true iff the CPU supports TBM.
* @since 0.9.21
*/
public boolean hasTBM()
{
return (CPUID.getECXCPUFlags() & (1 << 21)) != 0; //ECX Bit 21
}
/**
* @return true iff the CPU supports the AES-NI instruction set.
* @since 0.9.14
*/
public boolean hasAES() {
return (CPUID.getECXCPUFlags() & 0x2000000) != 0; //ECX Bit 25
return (CPUID.getECXCPUFlags() & (1 << 25)) != 0; //ECX Bit 25
}
public abstract boolean hasX64();
/**
* @return true iff the CPU supports the 64-bit support
* @since 0.9.21
*/
public boolean hasX64() {
return (CPUID.getExtendedEDXCPUFlags() & (1 << 29)) != 0; //Extended EDX Bit 29
}
}

31
core/java/src/freenet/support/CPUInformation/CPUInfo.java
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@ -62,10 +62,39 @@ public interface CPUInfo
* @return true iff the CPU support the SSE4A instruction set.
*/
public boolean hasSSE4A();
/**
* @return true iff the CPU supports the AVX instruction set.
* @since 0.9.21
*/
public boolean hasAVX();
/**
* @return true iff the CPU supports the AVX2 instruction set.
* @since 0.9.21
*/
public boolean hasAVX2();
/**
* @return true iff the CPU supports the full AVX512 instruction set.
* @since 0.9.21
*/
public boolean hasAVX512();
/**
* @return true iff the CPU supports TBM.
* @since 0.9.21
*/
public boolean hasTBM();
/**
* @return true iff the CPU supports the AES-NI instruction set.
* @since 0.9.14
*/
public boolean hasAES();
/**
* @return true iff the CPU supports the 64-bit support
* @since 0.9.21
*/
public boolean hasX64();
}

27
core/java/src/freenet/support/CPUInformation/IntelInfoImpl.java
View File

@ -45,7 +45,8 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
if (smodel != null)
return smodel;
throw new UnknownCPUException("Unknown Intel CPU; Family="+CPUID.getCPUFamily() + '/' + CPUID.getCPUExtendedFamily()+
", Model="+CPUID.getCPUModel() + '/' + CPUID.getCPUExtendedModel());
", Model="+CPUID.getCPUModel() + '/' + CPUID.getCPUExtendedModel()); //
}
private static String identifyCPU()
@ -148,7 +149,6 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isPentium4Compatible = true;
isPentiumMCompatible = true;
isCore2Compatible = true;
isX64 = true;
if (extmodel >= 2)
isCoreiCompatible = true;
}
@ -204,7 +204,6 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isPentium2Compatible = true;
isPentium3Compatible = true;
isPentiumMCompatible = true;
isX64 = true;
modelString = "Pentium M (Banias)";
break;
case 10:
@ -221,7 +220,6 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isPentium2Compatible = true;
isPentium3Compatible = true;
isPentiumMCompatible = true;
isX64 = true;
modelString = "Core (Yonah)";
break;
case 14:
@ -230,7 +228,6 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isPentium3Compatible = true;
isPentiumMCompatible = true;
isCore2Compatible = true;
isX64 = true;
modelString = "Penryn";
break;
@ -256,7 +253,6 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
// Some support SSE3? true for Pineview? TBD...
isCore2Compatible = false;
isPentium4Compatible = false;
isX64 = true;
modelString = "Atom";
break;
// Penryn 45 nm
@ -345,6 +341,19 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isBroadwellCompatible = true;
modelString = "Broadwell";
break;
// Ivy Bridge 22 nm
case 0x3e:
isSandyCompatible = true;
isIvyCompatible = true;
modelString = "Ivy Bridge";
break;
// Haswell 22 nm
case 0x3f:
isSandyCompatible = true;
isIvyCompatible = true;
isHaswellCompatible = true;
modelString = "Haswell";
break;
// following are for extended model == 4
// most flags are set above
@ -410,11 +419,9 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
modelString = "Pentium IV (90 nm)";
break;
case 4:
isX64 = true;
modelString = "Pentium IV (90 nm)";
break;
case 6:
isX64 = true;
modelString = "Pentium IV (65 nm)";
break;
default:
@ -432,8 +439,4 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
}
return modelString;
}
public boolean hasX64() {
return isX64;
}
}