- Fix main() model and family calculation
  - Add model string fetch from processor
  - AMD model string tweaks
This commit is contained in:
zzz
2014-09-29 13:05:38 +00:00
parent 0f298cf48e
commit a21e3cd842
3 changed files with 79 additions and 12 deletions

View File

@ -364,6 +364,9 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
// APUs // APUs
// http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors // http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors
// 1st gen Llano high perf / Brazos low power
// 2nd gen Trinity high perf / Brazos 2 low power
// 3rd gen Kaveri high perf / Kabini/Temash low power
case 18: { case 18: {
isK6Compatible = true; isK6Compatible = true;
isK6_2_Compatible = true; isK6_2_Compatible = true;
@ -371,7 +374,7 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isAthlonCompatible = true; isAthlonCompatible = true;
isAthlon64Compatible = true; isAthlon64Compatible = true;
isX64 = true; isX64 = true;
modelString = "AMD Llano/Trinity/Brazos model " + model; modelString = "AMD APU model " + model;
} }
break; break;
@ -388,10 +391,10 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
case 1: case 1:
// Case 3 is uncertain but most likely a Bobcat APU // Case 3 is uncertain but most likely a Bobcat APU
case 3: case 3:
modelString = "Bobcat APU"; modelString = "AMD Bobcat APU";
break; break;
default: default:
modelString = "AMD Bobcat model " + model; modelString = "AMD Bobcat APU model " + model;
break; break;
} }
} }
@ -408,8 +411,17 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isBulldozerCompatible = true; isBulldozerCompatible = true;
isX64 = true; isX64 = true;
switch (model) { switch (model) {
// 32 nm
case 1: case 1:
modelString = "Bulldozer FX-6000/8000"; modelString = "Bulldozer FX-6100/8100";
break;
// 32 nm
case 2:
modelString = "Bulldozer FX-6300/8300";
break;
// 28 nm ?
case 3:
modelString = "Bulldozer FX-6500/8500";
break; break;
default: default:
modelString = "AMD Bulldozer model " + model; modelString = "AMD Bulldozer model " + model;
@ -427,7 +439,14 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
isAthlon64Compatible = true; isAthlon64Compatible = true;
isBobcatCompatible = true; isBobcatCompatible = true;
isX64 = true; isX64 = true;
modelString = "AMD Jaguar model " + model; switch (model) {
case 0:
modelString = "Athlon 5350 APU";
break;
default:
modelString = "AMD Jaguar APU model " + model;
break;
}
} }
break; break;
} }

View File

@ -79,8 +79,11 @@ public class CPUID {
{ {
loadNative(); loadNative();
} }
//A class that can (amongst other things I assume) represent the state of the
//different CPU registers after a call to the CPUID assembly method /**
* A class that can (amongst other things I assume) represent the state of the
* different CPU registers after a call to the CPUID assembly method
*/
protected static class CPUIDResult { protected static class CPUIDResult {
final int EAX; final int EAX;
final int EBX; final int EBX;
@ -206,6 +209,40 @@ public class CPUID {
return c.EDX; return c.EDX;
} }
/**
* The model name string, up to 48 characters, as reported by
* the processor itself.
*
* @return trimmed string, null if unsupported
* @since 0.9.16
*/
static String getCPUModelName() {
CPUIDResult c = doCPUID(0x80000000);
long maxSupported = c.EAX & 0xFFFFFFFFL;
if (maxSupported < 0x80000004L)
return null;
StringBuilder buf = new StringBuilder(48);
int[] regs = new int[4];
for (int fn = 0x80000002; fn <= 0x80000004; fn++) {
c = doCPUID(fn);
regs[0] = c.EAX;
regs[1] = c.EBX;
regs[2] = c.ECX;
regs[3] = c.EDX;
for (int i = 0; i < 4; i++) {
int reg = regs[i];
for (int j = 0; j < 4; j++) {
char ch = (char) (reg & 0xff);
if (ch == 0)
return buf.toString().trim();
buf.append(ch);
reg >>= 8;
}
}
}
return buf.toString().trim();
}
/** /**
* Returns a CPUInfo item for the current type of CPU * Returns a CPUInfo item for the current type of CPU
* If I could I would declare this method in a interface named * If I could I would declare this method in a interface named
@ -237,9 +274,19 @@ public class CPUID {
System.out.println("**Failed to retrieve CPUInfo. Please verify the existence of jcpuid dll/so**"); System.out.println("**Failed to retrieve CPUInfo. Please verify the existence of jcpuid dll/so**");
} }
System.out.println(" **CPUInfo**"); System.out.println(" **CPUInfo**");
String mname = getCPUModelName();
if (mname != null)
System.out.println("CPU Model Name: " + mname);
System.out.println("CPU Vendor: " + getCPUVendorID()); System.out.println("CPU Vendor: " + getCPUVendorID());
System.out.println("CPU Family: " + getCPUFamily()); // http://en.wikipedia.org/wiki/Cpuid
System.out.println("CPU Model: " + getCPUModel()); int family = getCPUFamily();
int model = getCPUModel();
if (family == 15) {
family += getCPUExtendedFamily();
model += getCPUExtendedModel() << 4;
}
System.out.println("CPU Family: " + family);
System.out.println("CPU Model: " + model);
System.out.println("CPU Stepping: " + getCPUStepping()); System.out.println("CPU Stepping: " + getCPUStepping());
System.out.println("CPU Flags: 0x" + Integer.toHexString(getEDXCPUFlags())); System.out.println("CPU Flags: 0x" + Integer.toHexString(getEDXCPUFlags()));
@ -253,6 +300,7 @@ public class CPUID {
System.out.println("CPU has SSE4.1: " + c.hasSSE41()); System.out.println("CPU has SSE4.1: " + c.hasSSE41());
System.out.println("CPU has SSE4.2: " + c.hasSSE42()); System.out.println("CPU has SSE4.2: " + c.hasSSE42());
System.out.println("CPU has SSE4A: " + c.hasSSE4A()); System.out.println("CPU has SSE4A: " + c.hasSSE4A());
System.out.println("CPU has AES-NI: " + c.hasAES());
if(c instanceof IntelCPUInfo){ if(c instanceof IntelCPUInfo){
System.out.println("\n **Intel-info**"); System.out.println("\n **Intel-info**");
System.out.println("Is PII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible()); System.out.println("Is PII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible());

View File

@ -227,7 +227,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
case 0x17: case 0x17:
modelString = "Core 2 (45nm)"; modelString = "Core 2 (45nm)";
break; break;
// Nahalem 45 nm // Nehalem 45 nm
case 0x1a: case 0x1a:
isCoreiCompatible = true; isCoreiCompatible = true;
modelString = "Core i7 (45nm)"; modelString = "Core i7 (45nm)";
@ -246,7 +246,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
isCoreiCompatible = true; isCoreiCompatible = true;
modelString = "Xeon MP (45nm)"; modelString = "Xeon MP (45nm)";
break; break;
// Nahalem 45 nm // Nehalem 45 nm
case 0x1e: case 0x1e:
isCoreiCompatible = true; isCoreiCompatible = true;
modelString = "Core i5/i7 (45nm)"; modelString = "Core i5/i7 (45nm)";
@ -282,7 +282,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
case 0x2d: case 0x2d:
modelString = "Sandy Bridge EP"; modelString = "Sandy Bridge EP";
break; break;
// Nahalem 45 nm // Nehalem 45 nm
case 0x2e: case 0x2e:
modelString = "Xeon MP (45nm)"; modelString = "Xeon MP (45nm)";
break; break;