forked from I2P_Developers/i2p.i2p
CPUID:
- Fix main() model and family calculation - Add model string fetch from processor - AMD model string tweaks
This commit is contained in:
@ -364,6 +364,9 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
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// APUs
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// APUs
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// http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors
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// http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors
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// 1st gen Llano high perf / Brazos low power
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// 2nd gen Trinity high perf / Brazos 2 low power
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// 3rd gen Kaveri high perf / Kabini/Temash low power
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case 18: {
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case 18: {
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isK6Compatible = true;
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isK6Compatible = true;
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isK6_2_Compatible = true;
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isK6_2_Compatible = true;
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@ -371,7 +374,7 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
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isAthlonCompatible = true;
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isAthlonCompatible = true;
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isAthlon64Compatible = true;
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isAthlon64Compatible = true;
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isX64 = true;
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isX64 = true;
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modelString = "AMD Llano/Trinity/Brazos model " + model;
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modelString = "AMD APU model " + model;
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}
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}
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break;
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break;
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@ -388,10 +391,10 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
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case 1:
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case 1:
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// Case 3 is uncertain but most likely a Bobcat APU
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// Case 3 is uncertain but most likely a Bobcat APU
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case 3:
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case 3:
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modelString = "Bobcat APU";
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modelString = "AMD Bobcat APU";
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break;
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break;
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default:
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default:
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modelString = "AMD Bobcat model " + model;
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modelString = "AMD Bobcat APU model " + model;
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break;
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break;
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}
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}
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}
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}
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@ -408,8 +411,17 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
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isBulldozerCompatible = true;
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isBulldozerCompatible = true;
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isX64 = true;
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isX64 = true;
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switch (model) {
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switch (model) {
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// 32 nm
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case 1:
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case 1:
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modelString = "Bulldozer FX-6000/8000";
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modelString = "Bulldozer FX-6100/8100";
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break;
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// 32 nm
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case 2:
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modelString = "Bulldozer FX-6300/8300";
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break;
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// 28 nm ?
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case 3:
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modelString = "Bulldozer FX-6500/8500";
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break;
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break;
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default:
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default:
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modelString = "AMD Bulldozer model " + model;
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modelString = "AMD Bulldozer model " + model;
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@ -427,7 +439,14 @@ class AMDInfoImpl extends CPUIDCPUInfo implements AMDCPUInfo
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isAthlon64Compatible = true;
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isAthlon64Compatible = true;
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isBobcatCompatible = true;
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isBobcatCompatible = true;
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isX64 = true;
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isX64 = true;
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modelString = "AMD Jaguar model " + model;
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switch (model) {
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case 0:
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modelString = "Athlon 5350 APU";
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break;
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default:
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modelString = "AMD Jaguar APU model " + model;
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break;
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}
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}
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}
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break;
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break;
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}
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}
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@ -79,8 +79,11 @@ public class CPUID {
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{
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{
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loadNative();
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loadNative();
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}
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}
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//A class that can (amongst other things I assume) represent the state of the
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//different CPU registers after a call to the CPUID assembly method
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/**
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* A class that can (amongst other things I assume) represent the state of the
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* different CPU registers after a call to the CPUID assembly method
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*/
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protected static class CPUIDResult {
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protected static class CPUIDResult {
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final int EAX;
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final int EAX;
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final int EBX;
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final int EBX;
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@ -206,6 +209,40 @@ public class CPUID {
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return c.EDX;
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return c.EDX;
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}
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}
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/**
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* The model name string, up to 48 characters, as reported by
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* the processor itself.
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*
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* @return trimmed string, null if unsupported
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* @since 0.9.16
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*/
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static String getCPUModelName() {
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CPUIDResult c = doCPUID(0x80000000);
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long maxSupported = c.EAX & 0xFFFFFFFFL;
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if (maxSupported < 0x80000004L)
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return null;
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StringBuilder buf = new StringBuilder(48);
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int[] regs = new int[4];
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for (int fn = 0x80000002; fn <= 0x80000004; fn++) {
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c = doCPUID(fn);
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regs[0] = c.EAX;
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regs[1] = c.EBX;
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regs[2] = c.ECX;
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regs[3] = c.EDX;
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for (int i = 0; i < 4; i++) {
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int reg = regs[i];
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for (int j = 0; j < 4; j++) {
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char ch = (char) (reg & 0xff);
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if (ch == 0)
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return buf.toString().trim();
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buf.append(ch);
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reg >>= 8;
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}
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}
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}
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return buf.toString().trim();
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}
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/**
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/**
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* Returns a CPUInfo item for the current type of CPU
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* Returns a CPUInfo item for the current type of CPU
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* If I could I would declare this method in a interface named
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* If I could I would declare this method in a interface named
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@ -237,9 +274,19 @@ public class CPUID {
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System.out.println("**Failed to retrieve CPUInfo. Please verify the existence of jcpuid dll/so**");
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System.out.println("**Failed to retrieve CPUInfo. Please verify the existence of jcpuid dll/so**");
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}
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}
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System.out.println(" **CPUInfo**");
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System.out.println(" **CPUInfo**");
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String mname = getCPUModelName();
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if (mname != null)
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System.out.println("CPU Model Name: " + mname);
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System.out.println("CPU Vendor: " + getCPUVendorID());
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System.out.println("CPU Vendor: " + getCPUVendorID());
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System.out.println("CPU Family: " + getCPUFamily());
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// http://en.wikipedia.org/wiki/Cpuid
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System.out.println("CPU Model: " + getCPUModel());
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int family = getCPUFamily();
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int model = getCPUModel();
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if (family == 15) {
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family += getCPUExtendedFamily();
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model += getCPUExtendedModel() << 4;
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}
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System.out.println("CPU Family: " + family);
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System.out.println("CPU Model: " + model);
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System.out.println("CPU Stepping: " + getCPUStepping());
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System.out.println("CPU Stepping: " + getCPUStepping());
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System.out.println("CPU Flags: 0x" + Integer.toHexString(getEDXCPUFlags()));
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System.out.println("CPU Flags: 0x" + Integer.toHexString(getEDXCPUFlags()));
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@ -253,6 +300,7 @@ public class CPUID {
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System.out.println("CPU has SSE4.1: " + c.hasSSE41());
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System.out.println("CPU has SSE4.1: " + c.hasSSE41());
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System.out.println("CPU has SSE4.2: " + c.hasSSE42());
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System.out.println("CPU has SSE4.2: " + c.hasSSE42());
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System.out.println("CPU has SSE4A: " + c.hasSSE4A());
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System.out.println("CPU has SSE4A: " + c.hasSSE4A());
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System.out.println("CPU has AES-NI: " + c.hasAES());
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if(c instanceof IntelCPUInfo){
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if(c instanceof IntelCPUInfo){
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System.out.println("\n **Intel-info**");
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System.out.println("\n **Intel-info**");
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System.out.println("Is PII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible());
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System.out.println("Is PII-compatible: "+((IntelCPUInfo)c).IsPentium2Compatible());
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@ -227,7 +227,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
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case 0x17:
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case 0x17:
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modelString = "Core 2 (45nm)";
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modelString = "Core 2 (45nm)";
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break;
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break;
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// Nahalem 45 nm
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// Nehalem 45 nm
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case 0x1a:
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case 0x1a:
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isCoreiCompatible = true;
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isCoreiCompatible = true;
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modelString = "Core i7 (45nm)";
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modelString = "Core i7 (45nm)";
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@ -246,7 +246,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
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isCoreiCompatible = true;
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isCoreiCompatible = true;
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modelString = "Xeon MP (45nm)";
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modelString = "Xeon MP (45nm)";
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break;
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break;
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// Nahalem 45 nm
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// Nehalem 45 nm
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case 0x1e:
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case 0x1e:
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isCoreiCompatible = true;
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isCoreiCompatible = true;
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modelString = "Core i5/i7 (45nm)";
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modelString = "Core i5/i7 (45nm)";
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@ -282,7 +282,7 @@ class IntelInfoImpl extends CPUIDCPUInfo implements IntelCPUInfo
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case 0x2d:
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case 0x2d:
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modelString = "Sandy Bridge EP";
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modelString = "Sandy Bridge EP";
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break;
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break;
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// Nahalem 45 nm
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// Nehalem 45 nm
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case 0x2e:
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case 0x2e:
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modelString = "Xeon MP (45nm)";
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modelString = "Xeon MP (45nm)";
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break;
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break;
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